In recent years, the size of integrated circuits has decreased dramatically. As the size of these integrated circuits has shrunk they have commensurately become increasingly sensitive to noise. Integrated circuits have become more sensitive to noise for a whole host of reasons including: increasing interconnect densities within integrated circuits, faster clock rates utilized in conjunction with these integrated circuits and scaling threshold voltages. All of these factors degrade the signal-to-noise ratio in these circuits. Particularly, increasing interconnect densities imply a significant increase in coupling capacitance. Faster clock rates imply faster on-chip slew times. These two effects combine to make capacitive coupling a growing source of on-chip noise.
Additionally, many high-performance circuits try to speed up one edge transition (typically the falling edge), which usually occurs at the expense of the other edge transition, and assign logical evaluates to the faster edge. Circuits of this type usually have noise sensitivities directly related to the threshold voltages of the transistors responsible for the evaluation of these edge transitions. Threshold voltages are, however, scaling lower to maintain drive in the presence of similarly scaling supply voltages. These effects combine to produce more sources of on-chip noise due to switching circuits as well as less immunity to this noise.
Noise has two deleterious effects on digital circuits and designs, including microprocessor designs. Firstly, when noise acts against a normally static signal, it can transiently destroy the logical information carried by a static node in the circuit. If this ultimately results in incorrect machine states stored in one or more latches, functional failures may result. Secondly, when noise acts simultaneously with a switching node, this may be manifest as a change in the timing of the transition of the node, or other nodes.
In the past, to deal with noise issues of this type, designers of integrated circuits buffered the outputs of certain logic, or blocks of logic, within an integrated circuit. As the clock speeds of these integrated circuits have increased, however, these buffers were rendered obsolete, as they introduced an unacceptable amount of delay into these high speed circuits. For example, in a high speed circuit it may be desirable that paths in the circuit be comprised of less than ten stages of a gate, with a fan out of four or less. If buffers are utilized in this type of circuit to reduce noise, achieving this design goal may be difficult.
Noise behavior is an important characteristic of circuits, as it usually determines the fundamental limit of the performance of these circuits. Consequently, when designing an integrated circuit, a noise analysis of the integrated circuit is usually undertaken to assure the designers of the integrated circuit that the circuit does not exhibit undue sensitivity to noise, or that the integrated circuit will not experience failures due to noise related problems.
Noise analysis for analog circuits can be carried out using a direct method or an adjoint method. However, for system-level noise simulation for a complex integrated circuit, the direct method and the adjoint method are usually too inefficient to be practically utilized. Consequently, hierarchical noise analysis becomes an attractive alternative.
Conventional hierarchical noise analysis of VLSI circuits is usually based on a two step method, which may consist of 1) transistor level noise analysis creating a noise abstract of a logic block and 2) unit/chip level noise analysis using the noise abstracts created in step 1. Utilizing this technique, noise failures inside these logic blocks can only be detected at transistor level noise analysis, while noise failures at the unit/chip level can only be found at unit/chip level noise analysis. The main assumption in this analysis is that each block contains input pins, and output pins or bi-directional pins and only input pins or bi-directional pins feed the gates.
Typically in a hierarchical noise analysis methodology, circuit blocks are pre-characterized for noise tolerance and noise propagation. System-level noise is then analyzed using these block level noise models. More particularly, in certain hierarchical noise analysis techniques an integrated circuit, such as a microchip, is divided into a set of units. Usually, these units contain blocks of logic related to a similar activity.
For example, one unit may contain blocks of logic related to memory management, another unit may contain blocks of logic pertaining to floating point operations, and so forth. During hierarchical noise analysis of the microchip (or other integrated circuit) a transistor level noise analysis is performed on the blocks in the microchip to create a noise abstract for each of the blocks analyzed. Noise analysis can then be performed on specific units or the microchip as a whole using these individual unit noise abstracts.
Noise failures inside each of the blocks of logic can be detected while doing transistor level noise analysis in order to generate the abstract files, while noise failures at the unit or chip level can be found at the unit or chip level analysis. A main assumption in this type of analysis is that each block of logic contains input pins, output pins or bi-directional pins, and only input pins or bi-directional pins feed the gates of each block of logic.
In many cases, however, noise originating outside a block may be fed back to the block through an output of the block. This noise feedback through an output may result in a noise failure at a gate inside a block. For example, if a circuit topology is such that an output signal of a block also propagates to other logic inside the same block, a sufficiently large noise generated outside the block could be fed back through this output and could further proceed back through gates or logic in the block, resulting in a noise failure at a gate inside the block.
Thus, a need exists for systems and methods for hierarchical noise analysis that can account for noise failures in a block of circuitry caused by external sources attached to its output pins.